1. Field of the Invention
The present invention relates to an electrically erasable and programmable non-volatile semiconductor memory device and a manufacturing method thereof. More specifically, the present invention relates to a non-volatile semiconductor memory device having a structure enabling improved write/erase characteristics without decreasing its driving capability and a manufacturing method thereof.
2. Description of the Background Art
A memory device in which a data can be written freely and is electrically erasable has been known as a flash memory. An EEPROM (Electrically Erasable and Programmable) which can collectively erase electrically electric charges of written data, so-called flash memory, has been proposed in U.S. Pat. No. 4,868,619 or in "An In-System Reprogrammable 32K.times.8 CMOS Flash Memory" by Virgil Niles Kynett et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, October 1988.
By way of example, the above-mentioned flash memory will be described referring to FIGS. 10-24. FIG. 10 is a block diagram showing a general structure of the flash memory.
Referring to FIG. 10, a flash memory includes a memory cell array 100, an X address decoder 200, a Y gate 300, a Y address decoder 400, an address buffer 500, a write circuit 600, a sense amplifier 700, an input/output buffer 800, and a control logic 900.
Memory cell array 100 includes a plurality of memory transistors arranged in a matrix. X address decoder 200 and Y gate 300 are connected to memory cell array 100 respectively for selecting rows and columns of memory cell array 100.
Y address decoder 400 for applying data of column selection is connected to Y gate 300. Address buffer 500 for storing an address information temporarily is connected to each of X address decoder 200 and Y address decoder 400.
Write circuit 600 is connected to Y gate 300 for carrying out write operation at the time of data input/output. Also, sense amplifier 700 is connected to Y gate 300 for determining "0" or "1" based on a current value during data output. Input/output buffer 800 for storing input/output data temporarily is connected to write circuit 600 and sense amplifier 700.
Control logic 900 is connected to address buffer 500 and input/output buffer 800 for controlling an operation of the flash memory. The control logic 900 operates based on an chip enable signal, an output enable signal, and a program signal.
Referring to FIG. 11, connections between the memory transistors formed within memory cell array 100 and the above-mentioned respective elements will now be described. FIG. 11 is an equivalent circuit showing a schematic structure of memory cell array 100 shown in FIG. 10.
Referring to FIG. 11, a plurality of word lines WL.sub.1, WL.sub.2, . . . , WL.sub.i extending along rows and a plurality of bit lines BL.sub.1, BL.sub.2, . . . , BL.sub.j extending along columns are arranged such that respective word lines and bit lines are perpendicular to each other. Memory transistors Q.sub.11, Q.sub.12, . . . , Q.sub.ij, each having a floating gate electrode, are provided at crossings of respective word lines and bit lines.
Each memory transistor has its drain connected to each bit line. Also, each memory transistor has its control gate electrode connected to each word line. The memory transistors have their sources connected to respective source lines S.sub.1, S.sub.2, . . . , S.sub.i. The sources of memory transistor included in the same row are connected with each other, as shown in FIG. 11.
FIG. 12 is a cross sectional view of a memory transistor included in the above-described flash memory. The memory transistor shown in FIG. 12 is called a stacked gate-type memory transistor. FIG. 13 is a schematic plan view showing a planar layout of conventional stacked gate-type flash memory. FIG. 14 is a cross section taken along XIV--XIV line of FIG. 13. Referring to these figures, a structure of the conventional flash memory will now be described in more detail.
Referring to FIGS. 12 and 14, an n-type drain region 103 and an n-type source region 105 are formed spaced apart from each other in a p-type impurity region 104 provided at a main surface of a silicon substrate 101. A control gate electrode 113 and a floating gate electrode 109 are stacked on a region between drain region 103 and a source region 105 such that a channel is formed therebetween.
Floating gate electrode 109 is formed on a main surface of p-type impurity region 104 with a thin tunnel insulating film 107 of about 100 .ANG. in thickness interposed therebetween. Control gate electrode 113 is formed on floating gate electrode 109 with an interlayer insulating film 111 interposed therebetween so as to be isolated electrically from floating gate electrode 109. In this case, insulating layer 111 is formed stacked by a silicon oxide film 111a, a silicon nitride film 111b, and a silicon oxide film 111c.
Floating gate electrode 109 is formed of polycrystalline silicon. Control gate electrode 113 is formed of polycrystalline silicon or by a stacked film of polycrystalline silicon and a refractory metal. A sidewall insulating film 114 is formed on the side of the stacked structure of floating gate electrode 109, insulating layer 111 and control gate electrode 113. A silicon oxide film 115 and a silicon nitride film 116 are formed covering sidewall insulating film 114 and control gate electrode 113.
A smooth coat film 123 is formed on silicon nitride film 116 as shown in FIG. 14. A contact hole 122 is formed at a predetermined position (a region on drain region 103) of smooth coat film 123. A bit line 117 is formed to cover smooth coat film 123 and the inner surface of contact hole 122. Bit line 117 is connected electrically to drain region 103 via a drain contact 121.
Referring to FIG. 13, control gate electrodes (word lines) 113 are connected with each other and extend laterally (in the direction of rows). Bit lines 117 are arranged so as to cross word lines 113 perpendicularly. Bit lines 117 are connected electrically to drain regions 103 arranged longitudinally (in the direction of columns) via drain contacts 121.
Thus, drain regions 103 arranged longitudinally are connected with each other. Source region 105 is formed in a region surrounded by word line 113 and field oxide film 119 and extends along word line 113, as shown in FIG. 13. Each drain region 103 is also formed in the region surrounded by word line 113 and field oxide film 119.
An operation of the flash memory having the above structure will now be described referring to FIG. 12.
First, the write operation will be described referring to FIG. 12. In the write operation, a voltage V.sub.D of about 6 V--about 8 V is applied to drain region 103 and a voltage V.sub.G of about 10 V--about 15 V is applied to control gate electrode 113. Source region 105 and p-type impurity region 104 are held at the ground potential. Accordingly, a current of about several hundreds .mu.A flows in the channel region of the memory transistor.
At this time, electrons flow from source region 105 toward drain region 103. Among these electrons, the ones accelerated in the vicinity of drain region 103 come to have high energy in the vicinity of drain region 103, which are so-called channel hot electrons.
These electrons are injected into floating gate electrode 109, as indicated by an arrow 1 in FIG. 12, by an electric field generated by the voltage V.sub.G applied to control gate 113. Thus, electrons are stored in floating gate electrode 109. Accordingly, threshold voltage V.sub.th of the memory transistor becomes higher than a predetermined value. This state in which threshold voltage V.sub.th of the memory transistor becomes higher than the predetermined value is called written (programmed) state, which corresponds to "0".
Next, the erase operation will be described. In the erase operation, a voltage V.sub.S of about 10 V--about 12 V is applied to source region 105, while control gate electrode 113 and p-type impurity region 104 are held at the ground potential. At this time, drain region 103 is held at a floating state.
By an electric field generated by the voltage V.sub.S applied to source region 105, electrons in floating gate electrode 109 pass through the thin tunnel insulating film 107 by the tunnel effect, as indicated by an arrow 2 in FIG. 12.
Thus, threshold voltage V.sub.th of the memory transistor becomes lower than the predetermined value, because the electrons in floating gate electrode 109 are pulled out. This state in which threshold voltage V.sub.th of the memory transistor is lower than the predetermined value is called an erased state which corresponds to "1". Source regions 105 of respective memory transistors are connected with each other as shown in FIG. 13. Therefore, all the data of memory cells can be eased at a time by this erase operation.
The read operation will now be described. In the read operation, a voltage V.sub.G ' of about 5 V is applied to control gate electrode 113 and a voltage V.sub.D ' of about 1 V--about 2 V is applied to drain region 103. At this time, determination of "1" or "0" is carried out based on whether or not a current flows in the channel region of the memory transistor, in other words, the memory transistor is turned on or turned off.
A method of manufacturing the flash memory having the above structure will now be described referring to FIGS. 15-24. FIGS. 15-24 are sectional views showing the first to eighth steps of the process of manufacturing the flash memory. FIG. 19 is a sectional view taken along line XIX-XIX in FIG. 18, and FIG. 22 is a sectional view taken along line XXII--XXII in FIG. 21.
Referring to FIG. 15, a silicon oxide film 102 having a thickness of about 300 .ANG. is formed at a main surface of p-type &lt;100&gt; silicon substrate 101. Then, boron (B) is implanted through silicon oxide film 102 into a region where a p-type impurity region is to be formed at the main surface of silicon substrate 101 with 100 KeV and 1.0.times.10.sup.13 /cm.sup.2.
Referring to FIG. 16, p-type impurity region 104 is formed by diffusing the impurity (B) implanted into silicon substrate 101 at 1200.degree. C. for six hours. After that, silicon oxide film 102 is removed.
Referring to FIG. 17, a silicon oxide film 107 having a thickness of about 100 .ANG. is formed by the thermal oxidation method on the entire main surface of p-type impurity region 104. This will be tunnel insulating film 107.
A polycrystalline silicon layer 108 having a thickness of about 1000 .ANG. is formed by the CVD (Chemical Vapor Deposition) method on tunnel insulating film 107. This polycrystalline silicon layer 108 serves as floating gate electrode 109. Then, a resist pattern 106 patterned to have the shape of floating gate electrode 109 is formed on polycrystalline silicon layer 108.
Polycrystalline silicon layer 108 is etched using resist pattern 106 as a mask. FIG. 19 shows a sectional structure taken along line XIX--XIX of FIG. 18. After patterning polycrystalline silicon layer 108 as above, resist pattern 106 is removed.
Referring to FIG. 20, silicon oxide film 111a having a thickness of about 150 .ANG. is formed by the CVD method or the like on polycrystalline silicon layer 108. Then, silicon nitride film 111b having a thickness of about 150 .ANG. is formed by the CVD method or the like on silicon oxide film 111a. After that, silicon oxide film 111c having a thickness of about 20 .ANG. is formed on silicon nitride film 111b by thermal oxidation of silicon nitride film 111b.
Accordingly, insulating layer 111 is formed by those silicon oxide films 111a, 111c and silicon nitride film 111b. Polycrystalline silicon layer 110 having a thickness of about 2500 .ANG. is then formed by the CVD method or the like on silicon oxide film 111c. This polycrystalline silicon layer 110 serves as control gate electrode 113.
Referring to FIG. 21, a resist pattern 112 patterned into a predetermined shape is formed on polycrystalline silicon layer 110. Using the resist pattern 112 as a mask, polycrystalline silicon layer 110, silicon oxide film 111c, silicon nitride film 111b, silicon oxide film 111a, and polycrystalline silicon layer 108 are etched successively.
Thus, as shown in FIG. 21, control gate electrode 113 and floating gate electrode 109 are formed. A sectional view taken along line XXII--XXII in FIG. 21 is shown in FIG. 22.
Resist pattern 112 is then removed. As shown in FIG. 23, sidewall insulating film 114 is formed on the side of the stacked structure of floating gate electrode 109 and control gate electrode 113 by the CVD method, the etchback method or the like.
Silicon oxide film 115 is formed by the CVD method or the like on sidewall insulating film 114 and control gate electrode 113. Then, silicon nitride film 116 is formed by the CVD method or the like on silicon oxide film 115. After that, smooth coat film 123 is formed on silicon nitride film 116.
Referring to FIG. 24, contact hole 122 is formed by etching or the like at a position located on drain region 103. Then, an aluminum interconnection layer (bit line) 117 is formed by sputtering or the like on smooth coat film 123 and the inner surface of contact hole 122. Bit line 117 is connected electrically to drain region 103 via drain contact 121.
A smooth coat film 118 is formed again on aluminum interconnection layer 117. An aluminum interconnection layer 120 is formed on smooth coat film 118 by sputtering or the like. The flash memory is thus formed through the above-mentioned steps.
Such flash memory, however, has the following problem. The silicon oxide film is used as tunnel insulating film 107 in the above-described flash memory. At the time of erasing, electrons pass through thin tunnel insulating film 107 formed of the silicon oxide film by tunnel effect.
As a result, the silicon oxide film is deteriorated because of the passage of electrons through tunnel insulating film 107 formed of the silicon oxide film, and repeated write/erase operations cause breakdown of tunnel insulating film 107.
One method for restraining the breakdown induced by the passage of electrons by utilizing a nitrided oxide (oxinitride) film obtained by thermal nitriding of the silicon oxide film or a re-oxidized nitrided oxide film obtained by thermal oxidation of the nitrided oxide film has been proposed in "Extended Abstracts of the 22nd Conference on Solid State Devices and Materials," Sendai, 1990, pp. 171-174 and "Applied Physics Letters" 60(12l), 23 Mar. 1992, pp. 1489-1491.
As described in the above-mentioned references, the write/erase characteristics of the flash memory can be improved to some extent by thermally nitriding or thermally nitriding and thermally oxidizing the silicon oxide film, compared to the case when the silicon oxide film itself is used as tunnel insulating film 107. Even in this case, however, the following two problems exist.
The first problem will be described referring to FIGS. 25-27. FIG. 25 is a sectional view of the memory transistor when the nitrided oxide film or the re-oxidized nitrided oxide film is used as tunnel insulating film 107a. FIG. 26 shows the distribution of concentration of nitrogen included in tunnel insulating film 107a and regions in the vicinity thereof after the thermal nitriding or the thermal nitriding and thermal oxidation.
FIG. 27 shows the relationship between the cumulative failure rate (%) and the density of electric charges passed through the tunnel insulating film Qinj (C/cm.sup.2) in the case when the silicon oxide film is used as the tunnel insulating film (I) and when the re-oxidized nitrided oxide film is used as the tunnel insulating film (IIb, IIa).
In FIG. 27, (I) shows the case when electrons are passed in the same direction as in the erase operation utilizing as tunnel insulating film 107a the silicon oxide film obtained by thermal oxidation of the silicon substrate. (IIa) shows the case when electrons are passed in the direction reverse to that in the erase operation utilizing the re-oxidized nitrided oxide film as tunnel insulating film 107a. (IIb) shows the case when electrons are passed in the same direction as in the erase operation utilizing the re-oxidized nitrided oxide film as tunnel insulting film 107a. The above-mentioned cumulative failure rate (%) means the cumulative failure rate of devices failed by breakdown of tunnel insulating film 107a when the silicon oxide film or the re-oxidized nitrided oxide film is used as tunnel insulating film 107a.
Referring to FIG. 25, electrons are injected into floating gate electrode 109 from silicon substrate 101 by the channel hot electrons during writing of data. Referring to FIG. 26, tunnel insulating film 107a is formed by thermally nitriding and thermally oxidizing to the silicon oxide film after forming the silicon oxide film on silicon substrate 101.
Thus, as shown in FIG. 26, the top surface of tunnel insulating film 107a and an interface 125 between silicon substrate 101 and tunnel insulating film 107a are mainly nitrided. A nitrided portion D of silicon substrate 101 is thus formed at the interface between silicon substrate 101 and tunnel insulating film 107a.
Electrons are moved in the same direction as in the write operation and passed through tunnel insulating film 107a. The electrons pass through tunnel insulating film 107a via the above-mentioned nitrided portion D, as indicated by 1 in FIG. 26. The electrons are then injected into floating gate electrode 109.
As a result, as shown by (IIa) in FIG. 27, the value of electric charge density relative to the cumulative failure rate increases as compared to (I) when tunnel insulating film 107a is formed by the silicon oxide film. In other words, resistance of tunnel insulating film 107a is increased.
Referring again to FIG. 25, at the time of erasing, electrons are extracted from floating gate electrode 109 to source region 105 by tunnel effect within region B. The region where electrons pass through tunnel insulating film 107a by the tunnel effect is called "tunnel region" hereinafter in the present specification.
In this case, as indicated by 2 in FIG. 26, electrons pass through the nitrided portion on the top surface of tunnel insulating film 107a. Then, the electrons pass through tunnel insulating film 107a into source region 105. Thus, at the time of erasing, the electrons first pass through the nitrided portion of tunnel insulating film 107a itself, unlike the case of writing.
The electrons move in the same direction as in the above-described erase operation, and pass through tunnel insulating film 107a. Consequently, as shown by (IIb) in FIG. 27, the value of electric charge density relative to the cumulative failure rate becomes smaller than (I) when tunnel insulating film 107a is formed of the silicon oxide film. In other words, endurance of tunnel insulating film 107a is deteriorated.
As described above, if a thermally nitrided or thermally nitrided and thermally oxidized tunnel insulating film 107a is used, when electrons are moved from silicon substrate 101 to floating gate electrode 109 (in the direction of writing), endurance of the tunnel insulating film 107a improves, but when electrons are moved from floating gate electrode 109 to source region 105 (in the direction of erasing), endurance of tunnel insulating film 107a deteriorates as compared to the case when the silicon oxide film is used.
Therefore, even when thermally nitrided or thermally nitrided and thermally oxidized tunnel insulating film 107a is used, the write/erase characteristics of the flash memory cannot be improved sufficiently.
The second problem will now be described referring to FIGS. 28 and 29. FIG. 28 is a plan view showing a memory transistor including thermally nitrided or thermally nitrided and thermally oxidized tunnel insulating film 107a. FIG. 29 shows a sectional structure taken along line XXIX--XXIX in FIG. 28 and the distribution of nitrogen concentration in the top surface of tunnel insulating film 107a.
Referring to FIG. 28, when tunnel insulating film 107a is thermally nitrided or the thermally nitrided and thermally oxidized, the entire top surface of tunnel insulating film 107a is nitrided. Thus, a portion on a channel region 124 in the memory transistor is also nitrided. More specifically, as shown in FIG. 29, the entire top surface of tunnel insulating film 107a including the region on channel region 124 are nitrided almost uniformly.
The following problem is generated by nitriding the portion of tunnel insulating film 107a located on channel region 124. As disclosed in "International Electron Device Meeting" 1991, pp. 649-652, driving capability of the transistor at low voltages decreases when tunnel insulating film 107a having the entire surface thereof nitrided is used. In other words, when the nitrided oxide film or the re-oxidized nitrided oxide film is used as tunnel insulating film 107a, driving capability of the memory transistor at low voltages is deteriorated.